Samsung Released a New Generation of 3nm Gate Full Ring Process, Gaining a Leading Position in GAA Process

In recent years, in the fierce market competition environment, Samsung has shifted its business focus to logic process OEM. At the recent US chapter of SFF (Samsung foundry Forum), Samsung announced four FinFET processes, covering 7Nm to 4nm. At the same time, a new generation of 3nm gate all around (GAA) process was released. Compared with 7Nm technology, Samsung's 3gae process will reduce the area by 45%, reduce the power consumption by 50% and improve the performance by 35%. Samsung said that the first 3nm chips were mainly for smartphones and other mobile devices.

At present, the advanced semiconductor manufacturing process has entered below the 10nm node. TSMC took the lead in mass production of the 7Nm process last year, but there is no EUV lithography process. Samsung chose to directly enter the 7Nm EUV process, so it is one year behind TSMC in progress. However, Samsung is determined to catch up with TSMC in the 3nm process. According to Samsung's Roadmap, they will mass produce 3nm process in 2021, and TSMC will almost enter the 3nm node at that time. However, TSMC has not defined the technical details of 3nm, which means that Samsung has gained a leading position in GAA process.

Ryan SangHyun Lee, deputy general manager of Samsung wafer foundry business market, said that Samsung has been developing GAA technology since 2002 and has manufactured mbcfet (multi bridge channel fet) by using nano chip equipment. This technology can significantly enhance the performance of transistors, so as to realize the manufacturing of 3nm process.However, TSMC is also actively promoting the 3nm process. In 2018, TSMC announced that it plans to invest NT $600 billion to build a 3nm plant, hoping to start construction in 2020 and start mass production as soon as the end of 2022. It has been reported that TSMC 3nm process technology has entered the experimental stage and has made a new breakthrough in GAA technology. TSMC pointed out in its first quarter financial report that its 3nm technology has entered the stage of comprehensive development.In fact, TSMC and Samsung Electronics have been competing on advanced technology for many years. This year, they will compete mainly on 3nm technology. However, neither TSMC, Samsung nor Intel mentioned the semiconductor process roadmap after 3nm.

Because after the processing linewidth of integrated circuits reaches 3nm, it will enter the category of mesoscopic physics. The data show that mesoscopic materials, on the one hand, contain a certain amount of particles, which can not be solved only by Schrodinger equation; On the other hand, the number of particles is not large enough to ignore statistical fluctuation. This makes the further development of integrated circuit technology encounter many physical obstacles. In addition, the power consumption caused by the increase of leakage current is also difficult to solve.Therefore, the 3nm process is also known as the physical limit of semiconductors. However, in the decades before the development of the semiconductor industry, the industry has repeatedly encountered the so-called process limit problem, but these technical necks have been broken again and again.Ryan Lee, vice president of marketing of Samsung OEM business, also predicted the future of Samsung chips: the development of GAA technology may make 2nm or even 1nm process possible. Although Samsung is not sure what kind of structure it will adopt, it still believes that such technology will appear. In other words, Samsung plans to use GAA process to challenge physical limits.